Product Summary
The 74HC165N is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC165N is a 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 tp Q1 to Q2, etc.) with each positive-going clock transition. This feature of the 74HC165N allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The applications of the 74HC165N include Parallel-to-serial data conversion.
Parametrics
74HC165N absolute maximum ratings: (1)tPHL/ tPLH, propagation delay CP to Q7, Q7: 16ms when CL = 15 pF; VCC = 5 V; PL to Q7, Q7: 15ns when CL = 15 pF; VCC = 5 V; D7 to Q7, Q7: 11ns when CL = 15 pF; VCC = 5 V; (2)fmax, maximum clock frequency: 56MHz; (3)CI, input capacitance: 3.5pF; (4)CPD, power dissipation capacitance per package: 35pF.
Features
74HC165N features: (1)Asynchronous 8-bit parallel load; (2)Synchronous serial input; (3)Output capability: standard; (4)ICC category: MSI.
Diagrams
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74HC165N |
Other |
Data Sheet |
Negotiable |
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74HC165N,652 |
NXP Semiconductors |
Counter Shift Registers 8BIT SHIFT REGISTER PAR-IN/SERIAL-OUT |
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